Linty Documentation


CNES Cutom Coverage by Linty Rules

ID Title Automatable Coverage (full / high / low / none) Comments Linty Rules
CNE‑00100 Identification of active low signal no none    
CNE‑00200 Unsuitability of frequency in clock name yes full   VHDL1070: Clock names should not contain frequency information

CNE‑00300 Unsuitability of pin number in signal name yes full   VHDL212: Top-level entity port names should not contain any pin number

CNE‑00400 Name of testbench entity yes full   VHDL010: Entity names should comply with a naming convention

CNE‑00500 Convention for signal naming no none    
CNE‑00600 Convention for constant naming no none    
CNE‑00700 Convention for process naming no none    
CNE‑00800 Convention for generic ports no none    
CNE‑00900 Convention for custom type naming no none    
CNE‑01000 Identification of variable name yes full   VHDL116: Variable names should comply with a naming convention

CNE‑01100 Identification of ports direction inside entity port name yes full   VHDL118: Port names should comply with a naming convention

CNE‑01200 Identification of process label yes full   VHDL1035: Process labels should comply with a naming convention

CNE‑01300 Identification of constant name yes full   VHDL117: Constant names should comply with a naming convention

CNE‑01400 Identification of generic port name yes full   VHDL120: Generic parameter names should comply with a naming convention

CNE‑01500 Identification of custom type name yes full   VHDL122: Type names should comply with a naming convention

CNE‑01600 Identification of package element yes low Only package name is checked for now VHDL171: Package names should comply with a naming convention

CNE‑01700 Identification of rising edge detection signal no none    
CNE‑01800 Identification of falling edge detection signal no none    
CNE‑01900 Identification of registered signals yes none    
CNE‑02000 Identification of Finite State Machine yes full   VHDL1003: FSM state signal names should comply with a naming convention

CNE‑02100 Name of RTL architectures yes high   VHDL005: Architecture names should comply with a naming convention

CNE‑02200 Name of configuration entity no none    
CNE‑02300 Preservation of clock name yes high   VHDL1061: Clock names should be preserved across the design

CNE‑02400 Preservation of reset name yes high   VHDL1062: Reset names should be preserved across the design

CNE‑02500 Length of entities name yes full   VHDL010: Entity names should comply with a naming convention

CNE‑02600 Length of signals name yes full   VHDL119: Signal names should comply with a naming convention

CNE‑02700 Number of lines in file yes full   VHDL033: Files should not have too many lines of code

CNE‑02800 Software VHDL generator in header of file no none    
CNE‑02900 File name in the header of file yes full   VHDL239: File header should match a template

CNE‑03000 Creation date in the header of file yes full   VHDL239: File header should match a template

CNE‑03100 Project name in the header of file yes full   VHDL239: File header should match a template

CNE‑03200 Author in the header of file yes full   VHDL239: File header should match a template

CNE‑03300 Functional description in the header of file yes high   VHDL239: File header should match a template

CNE‑03400 Naming convention in the header of file yes full   VHDL239: File header should match a template

CNE‑03500 Functional limitation in the header of file yes high   VHDL239: File header should match a template

CNE‑03600 Current version number in the header of file yes full   VHDL239: File header should match a template

CNE‑03700 Author of modification(s) in the header of file yes full   VHDL239: File header should match a template

CNE‑03800 Version history in the header of file yes full   VHDL239: File header should match a template

CNE‑03900 Reason(s) of modification(s) in the header of file yes full   VHDL239: File header should match a template

CNE‑04000 Functional impact(s) of modifications in the header of file yes full   VHDL239: File header should match a template

CNE‑04100 Functional description of modifications in the header of file yes full   VHDL239: File header should match a template

CNE‑04200 Applicable license in header of file yes full   VHDL239: File header should match a template

CNE‑04300 Company coding in the header of file yes full   VHDL239: File header should match a template

CNE‑04400 Company owner of code in the header of file yes full   VHDL239: File header should match a template

CNE‑04500 Reset registers yes none    
CNE‑04600 Finite State Machine coding style no none Generic rule for CNE-04700, CNE-4800 VHDL1007: Find finite state machine (FSM) signals and their usage

CNE‑04700 Finite State Machine single process based yes none    
CNE‑04800 Finite State Machine two processes based yes none    
CNE‑04900 Use of clock signal yes full   VHDL1012: Clock signals not used as clock of a flip-flop should be reviewed

CNE‑05000 Multiplexor coding style no none Generic rule for CNE-05100, CNE-05200  
CNE‑05100 Multiplexor single process based yes none    
CNE‑05200 Multiplexor direct assertion based yes none    
CNE‑05300 Hierarchical level of entity yes none    
CNE‑05400 Number of nested packages yes full   VHDL152: Packages should not be too deeply nested

CNE‑05500 Dimension of array yes full   VHDL182: Avoid using arrays with too many dimensions