Linty Documentation


CNES Coverage by Linty Rules

ID Title Automatable Coverage (full / high / low / none) Comments Linty Rules
STD‑00100 VHDL object naming convention yes full   VHDL181: Alias names should comply with a naming convention

VHDL171: Package names should comply with a naming convention

VHDL187: “for” generate statement labels should comply with a naming convention

VHDL173: Instance names should comply with a naming convention

VHDL131: Procedure names should comply with a naming convention

VHDL010: Entity names should comply with a naming convention

VHDL130: Function names should comply with a naming convention

VHDL005: Architecture names should comply with a naming convention

VHDL006: Configuration names should comply with a naming convention

VHDL120: Generic parameter names should comply with a naming convention

VHDL122: Type names should comply with a naming convention

VHDL121: Subtype names should comply with a naming convention

VHDL117: Constant names should comply with a naming convention

VHDL116: Variable names should comply with a naming convention

VHDL118: Port names should comply with a naming convention

VHDL119: Signal names should comply with a naming convention

VHDL1026: Reset signal names should comply with a naming convention

VHDL1035: Process labels should comply with a naming convention

VHDL1009: Clock signal names should comply with a naming convention

VHDL309: “if” generate statement labels should comply with a naming convention

VHDL310: “case” generate statement labels should comply with a naming convention

STD‑00200 Name of clock signal yes full   VHDL1009: Clock signal names should comply with a naming convention

STD‑00300 Name of reset signal yes full   VHDL1026: Reset signal names should comply with a naming convention

STD‑00400 Label for process yes full   VHDL213: Processes should be identified by labels

STD‑00500 Name of signal relation with behaviour no none    
STD‑00600 VHDL file extension yes full   VHDL180: File name should comply with a naming convention

STD‑00701 Preservation of signal name inside an entity yes none    
STD‑00800 File name convention yes full   VHDL180: File name should comply with a naming convention

VHDL010: Entity names should comply with a naming convention

STD‑00900 File name of an entity yes full   VHDL180: File name should comply with a naming convention

VHDL010: Entity names should comply with a naming convention

STD‑01000 Number of entities per file yes full   VHDL218: A file should not define more than one entity

STD‑01100 Number of architectures in files yes full   VHDL019: Each file should define only one single architecture

STD‑01200 Number of statements per line yes full   VHDL161: Statements should be on separate lines

VHDL126: Multiple declarations should not be written on the same line

STD‑01300 Number of ports declaration per line yes full   VHDL137: Only one port should be declared or mapped on each line

STD‑01400 Instantiation of components yes full   VHDL189: End block identifier should be repeated at the end

VHDL188: Instantiations should be done by name, not by position

STD‑01500 Entity ports convention no none Generic rule of STD-01600 and STD-01700  
STD‑01600 Entity port sort no none    
STD‑01700 Entity special ports yes none    
STD‑01800 Primitive isolation no none    
STD‑01900 Indentation of source code yes low   VHDL210: Port clauses should be properly formatted

STD‑02000 Indentation style yes full   HDL004: Tabulation characters should not be used

STD‑02100 Compactness of VHDL source code yes full   VHDL033: Files should not have too many lines of code

VHDL149: Extended identifiers should not be used

STD‑02200 Version control in header of file yes full   VHDL239: File header should match a template

STD‑02300 Copyright information in the header of file yes full   VHDL239: File header should match a template

STD‑02400 Creation information in the header of the file yes full   VHDL239: File header should match a template

STD‑02500 Functional information in the header of file yes full   VHDL239: File header should match a template

STD‑02600 IEEE libraries preference yes full   VHDL211: Synopsys “std_logic_arith”, “std_logic_signed” and “std_logic_unsigned” libraries should not be used

STD‑02700 Default language yes full Headers and comments checked. Not possible to check code (such as entity names, signal names, etc.). It would lead to too many false positives. VHDL225: Comments should be written in a specified language / Commented-out code should be removed

STD‑02800 Comment strategy yes full Comment density only as the relevance of comments cannot be automated  
STD‑02900 Comments for entity ports yes full   VHDL163: Entity ports should be commented

STD‑03000 Comments for objects declaration and statements yes high   VHDL160: Declarations should be commented

VHDL207: Processes should be commented

STD‑03100 Dead VHDL code yes high   VHDL135: All declared parameters should be used in the corresponding function/procedure

VHDL134: All declared elements should be used in their corresponding scope

VHDL1052: Unused generate blocks should be removed

VHDL1050: Unused entities should be removed

VHDL1051: Unused architectures should be removed

STD‑03200 Unused output ports components management yes low Does not check unused ports VHDL138: All output ports (and optionally all input ports) of a component should be mapped

STD‑03300 Buffer port type yes full   VHDL025: Only allowed port modes should be used: ‘in’, ‘out’ and, for top-level entities only, ‘inout’

STD‑03400 Top level ports yes full   VHDL026: Only allowed port types should be used

STD‑03500 Record type for top level entity ports yes full   VHDL026: Only allowed port types should be used

STD‑03600 Reset sensitive level yes full   VHDL1027: Active-high resets should be preferred over active-low resets

VHDL1028: Active-low resets should be preferred over active-high resets

STD‑03700 Reset assertion and deassertion yes none    
STD‑03800 Synchronous elements initialization yes none    
STD‑03900 State machine type definition yes full   VHDL1005: FSM states should be encoded using enumerated type

STD‑04000 State machine case enumeration completion yes full   VHDL003: Each case statement should define an “others” clause

STD‑04100 Clock domain crossing yes full   HDL1000: All clock domains should be reviewed

HDL1001: All clock domain crossings should be reviewed

STD‑04200 Clock domain crossing handshake based yes none    
STD‑04300 Clock domain crossing FIFOs based yes none    
STD‑04400 Clock management module yes full   VHDL1055: All clocks should be generated within a unique clock management module

STD‑04500 Unsuitability of Clock Reassignment yes full   VHDL1012: Clock signals not used as clock of a flip-flop should be reviewed

STD‑04600 Clock domain number in the design yes full   HDL1002: The number of clock domains per design should be as low as possible

STD‑04700 Number of clock domains per modules yes high   VHDL1049: An entity should not use multiple clocks

STD‑04800 Clock edge sensitivity yes full   VHDL1010: Falling should be preferred over rising to detect clock transitions

VHDL1011: Rising should be preferred over falling to detect clock transitions

STD‑04900 Edge detection best practice yes none    
STD‑05000 Sensitivity list for synchronous processes yes full   VHDL1037: The sensitivity list of a process should be minimal

VHDL1072: The sensitivity list of a process should be complete

STD‑05100 Metastability management yes none    
STD‑05200 Output signal registration yes full   HDL1008: All output signals of top-level module should be registered

STD‑05300 Sensitivity list for combinational processes yes full   VHDL1037: The sensitivity list of a process should be minimal

VHDL1072: The sensitivity list of a process should be complete

STD‑05400 Unsuitability of internal tristate yes full   VHDL224: Internal tristates should not be used

STD‑05500 Unsuitability of latches yes full   VHDL140: Concurrent assignments should be complete to avoid undesired latch inference

VHDL1036: “if” statements should always contain an “else” statement in combinational processes to avoid undesired latch inference

VHDL1037: The sensitivity list of a process should be minimal

VHDL1063: Latches should be removed

VHDL1072: The sensitivity list of a process should be complete

STD‑05600 Unsuitability of combinational feedbacks yes full   HDL1003: Combinatorial loops should be removed

STD‑05700 Unsuitability of gated clocks yes none    
STD‑05800 Use of VHDL types in RTL design yes full   VHDL1005: FSM states should be encoded using enumerated type

VHDL303: Only synthesizable types should be used in design

STD‑05900 Range for integers yes full   VHDL029: ‘integer’, ‘natural’ and ‘positive’ declarations should have range constraint

STD‑06000 Range direction for arrays yes full   VHDL164: Range direction in array definitions should always be the same

STD‑06100 Range direction for std_logic_vector yes full   VHDL036: Vector direction in ranges should always be the same

STD‑06200 Management of numeric values yes high   VHDL023: Hardcoded numeric values should be used only in “constant” or “generic”

STD‑06300 Unsuitability of variables in RTL design yes low   VHDL308: Variables should not be used

VHDL190: Variables should only be used in processes, functions and procedures

STD‑06400 Error mitigation strategy no none Generic rule  
STD‑06500 Counters end of counting yes none    
STD‑06600 Dimension of comparison elements yes full   VHDL1066: Objects of different lengths should not be compared

STD‑06700 Unsuitability of wait statement in RTL design yes full   VHDL183: Non-synthesizable statements should not be used in design

STD‑06800 Unsuitability of signal initialization in declaration section yes full   VHDL032: Signals should not be initialized in their declaration

STD‑06900 Unsuitability of procedures and functions in RTL design yes full   VHDL206: Functions and procedures should not be used in design

STD‑07000 Maximum depths of nested objects yes high   VHDL172: Conditional branching statements (“if”, “case”, “while” and “for” loops) should not be too deeply nested

VHDL152: Packages should not be too deeply nested

STD‑07100 Simulation ending yes none    
STD‑07200 Use of procedures and functions in testbenches no none Generic rule  
STD‑07300 Use of wait statement in testbenches yes none