# Release Notes

## 4.0.1

Released on March 18th, 2024.

### Release Notes

It fixes the following issues:
* Not possible to render design hierarchy graph with blackboxes
* Issues are not always displayed in [Linty HDL Designer](https://hdl-designer.linty-services.com/) on Windows

### Upgrade Notes

* Keep your current version of the linty-scanner: 4.0.0
* Upgrade [Linty HDL Designer](https://hdl-designer.linty-services.com/) to 4.0.4


## 4.0.0

Released on December 17th, 2024.

### Release Notes

* Reset domain crossings (RDC) detection
* Fully rewritten Verilog/SystemVerilog plugin:
    * Parses all standards
    * Runs much faster
    * Adds 136 new rules, most of which are included in the free version
      of [Linty HDL Designer](https://hdl-designer.linty-services.com/)
* Rules and reports on FSM now also apply to Verilog and mixed-language projects
* Built on [SonarQube 10.7](https://www.sonarsource.com/products/sonarqube/whats-new/sonarqube-10-7/)

#### New rules

145 new rules:

* HDL: [8 new rules](https://demo.linty-services.com/coding_rules?available_since=2024-05-18&languages=hdl) on reset
  domains, RDC, input port registration, etc.
* VHDL: [1 new rule](https://demo.linty-services.com/coding_rules?available_since=2024-05-18&languages=vhdl) on not
  using reserved words in future VHDL standards as identifiers
* Verilog/SystemVerilog: [136 new rules](https://demo.linty-services.com/coding_rules?available_since=2024-05-18&languages=verilog)
on implicit casts and conversions, overflows and many more

### Upgrade notes

The following rules now apply to VHDL, Verilog/SystemVerilog and mixed-language designs:

* VHDL1057 => [HDL1016 - The number of reset domains per design should be as low as possible](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1016&rule_key=hdl%3AHDL1016)
* VHDL1058 => [HDL1018 - All global resets should be generated within a unique reset management module](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1018&rule_key=hdl%3AHDL1018)
* VHDL1059 => [HDL1020 - Reset management modules should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1020&rule_key=hdl%3AHDL1020)
* VHDL1060 => [HDL1019 - Clock management module and reset management module should be the same module](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1019&rule_key=hdl%3AHDL1019)
* VHDL1007 => [HDL1023 - Track finite state machines (FSM)](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1023&rule_key=hdl%3AHDL1023)
* VHDL1020 => [HDL1024 - FSM should have a minimal number of states](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1024&rule_key=hdl%3AHDL1024)
* VHDL1019 => [HDL1025 - FSM should not have too many states](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1025&rule_key=hdl%3AHDL1025)
* VHDL1021 => [HDL1026 - FSM should not have too many output signals](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1026&rule_key=hdl%3AHDL1026)
* VHDL1022 => [HDL1027 - FSM should not have too many input signals](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1027&rule_key=hdl%3AHDL1027)
* VHDL1003 => [HDL1028 - FSM state signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1028&rule_key=hdl%3AHDL1028)
* VHDL1023 => [HDL1029 - FSM should not have states that can target too many other states](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1029&rule_key=hdl%3AHDL1029)

Activate corresponding HDL rules if some of these VHDL rules were activated in your VHDL quality profiles.

## 3.1.0

Released on May 18th, 2024.

### Release Notes

This release focuses on architecture with new rules and design hierarchy graph in
[Linty HDL Designer](https://hdl-designer.linty-services.com/). It also provides the ability to
[generate documentation as HTML](html_report).

![Design Hierarchy](../assets/images/release-notes/design-hierarchy.png)

Built on [SonarQube 10.5.1](https://www.sonarsource.com/products/sonarqube/whats-new/sonarqube-10-5/).

#### New rules

* [VHDL316 - An entity should not have too many ports](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL316&rule_key=vhdl%3AVHDL316)
* [VHDL317 - A function or procedure should not have too many parameters](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL317&rule_key=vhdl%3AVHDL317)
* [VHDL318 - Generics should not define default values](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL318&rule_key=vhdl%3AVHDL318)
* [VHDL1073 - All assertions failing as note should be reviewed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1073&rule_key=vhdl%3AVHDL1073)
* [VHDL1074 - All assertions failing as warning should be reviewed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1074&rule_key=vhdl%3AVHDL1074)
* [VHDL1075 - All assertions failing as error should be reviewed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1075&rule_key=vhdl%3AVHDL1075)
* [HDL1012 - A module should not depend on too many other modules](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1012&rule_key=hdl%3AHDL1012)
* [HDL1015 - Clock management module should be instantiated in top module](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1015&rule_key=hdl%3AHDL1015)

#### Rules that now apply to VHDL, Verilog/SystemVerilog and mixed-language designs

* VHDL1055 => [HDL1013 - All clocks should be generated within a unique clock management module](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1013&rule_key=hdl%3AHDL1013)
* VHDL1056 => [HDL1014 - Clock management module should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1014&rule_key=hdl%3AHDL1014)

### Upgrade Notes

Activate [HDL1013](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1013&rule_key=hdl%3AHDL1013)
and [HDL1014](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1014&rule_key=hdl%3AHDL1014)
to replace removed VHDL1055 and VHDL1056 rules.

## 3.0.0

Released on February 8th, 2024.

### Release Notes

Linty detects all clock domain crossings (CDC). You can now easily browse, investigate, accept or fix any clock domain
crossing.

![img.png](../assets/images/bugfinder/cdc.png)

Built on [SonarQube 10.3.0](https://www.sonarsource.com/products/sonarqube/whats-new/sonarqube-10-3/).

#### New rules

* [HDL1000 - All clock domains should be reviewed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1000&rule_key=hdl%3AHDL1000)
* [HDL1001 - All clock domain crossings should be reviewed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1001&rule_key=hdl%3AHDL1001)
* [HDL1004 - Top-level input ports should not be used within multiple clock domains](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1004&rule_key=hdl%3AHDL1004)

#### Rules that now apply to VHDL, Verilog/SystemVerilog and mixed-language designs

A new language has been created: [HDL](https://demo.linty-services.com/coding_rules?languages=hdl). HDL rules apply to
VHDL, Verilog/SystemVerilog and mixed-language designs.

The following rules have been extended to apply to VHDL and Verilog/SystemVerilog and mixed-language designs.
You should activate those rules in replacement of the related (and removed) VHDL/Verilog rules:

* VHDL1054 => [HDL1002 - The number of clock domains per design should be as low as possible](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1002&rule_key=hdl%3AHDL1002)
* VHDL1048 => [HDL1003 - Combinatorial loops should be removed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1003&rule_key=hdl%3AHDL1003)
* VHDL1000 => [HDL1005 - All input ports should be connected](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1005&rule_key=hdl%3AHDL1005)
* VHDL1001 => [HDL1006 - All output ports should be connected](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1006&rule_key=hdl%3AHDL1006)
* VHDL1002 => [HDL1007 - All inout ports should be connected](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1007&rule_key=hdl%3AHDL1007)
* VHDL1004 => [HDL1008 - All output signals of top-level module should be registered](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1008&rule_key=hdl%3AHDL1008)
* VHDL1016 => [HDL1009 - All output signals of low-level modules should be registered](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1009&rule_key=hdl%3AHDL1009)
* VHDL1017 => [HDL1010 - Output signals should not be constant](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1010&rule_key=hdl%3AHDL1010)
* VHDL1018 => [HDL1011 -Ports should not be directly connected](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1011&rule_key=hdl%3AHDL1011)
* VHDL177 and VERILOG007 => [HDL001 - Files should contain an empty new line at the end](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL001&rule_key=hdl%3AHDL001)
* VHDL179 and VERILOG006 => [HDL002 - End-line characters should be consistent](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL002&rule_key=hdl%3AHDL002)
* VHDL178 and VERILOG010 => [HDL003 - Lines should not end with trailing whitespaces](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL003&rule_key=hdl%3AHDL003)
* VHDL034 and VERILOG011 => [HDL004 - Tabulation characters should not be used](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL004&rule_key=hdl%3AHDL004)
* VHDL017 and VERILOG009 => [HDL005 - Lines should not be too long](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL005&rule_key=hdl%3AHDL005)

#### Linty Scanner adds compatibility to Windows and Mac

Linty analyses can now be run from [Linux, Windows and Mac machines](http://localhost:4000/scan.html#requirements)
built on AMD, Intel or ARM processors.

### Upgrade Notes

Please, ask for a new license key before upgrading to this latest version.

## 2.1.0

Released on November 25th, 2023.

### Release Notes

You can now check more than 200 rules on your VHDL code.

Built on the latest [SonarQube 10.3.0](https://www.sonarsource.com/products/sonarqube/whats-new/sonarqube-10-3/).

#### VHDL

12 new rules have been added:

* [VHDL1063 - Latches should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1063&rule_key=vhdl%3AVHDL1063)
* [VHDL1064 - Choices outside of range should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1064&rule_key=vhdl%3AVHDL1064)
* [VHDL1065 - Choices should not overlap](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1065&rule_key=vhdl%3AVHDL1065)
* [VHDL1066 - Objects of different lengths should not be compared](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1066&rule_key=vhdl%3AVHDL1066)
* [VHDL1067 - Range should not be empty](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1067&rule_key=vhdl%3AVHDL1067)
* [VHDL1068 - Functions should always return a value](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1068&rule_key=vhdl%3AVHDL1068)
* [VHDL1069 - Signals and variables should be assigned a value before being used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1069&rule_key=vhdl%3AVHDL1069)
* [VHDL1070 - Clock names should not contain frequency information](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1070&rule_key=vhdl%3AVHDL1070)
* [VHDL305 - "while" loops should not be used for synthesis](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL305&rule_key=vhdl%3AVHDL305)
* [VHDL306 - Only one single architecture per entity should be defined](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL306&rule_key=vhdl%3AVHDL306)
* [VHDL307 - Code should be properly commented](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL307&rule_key=vhdl%3AVHDL307)
* [VHDL308 - Variables should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL308&rule_key=vhdl%3AVHDL308)

VHDL187 has been split into three rules to allow different naming conventions for `for`, `if` and `case` generate
statements:

* [VHDL187 - "for" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL187&rule_key=vhdl%3AVHDL187)
* [VHDL309 - "if" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL309&rule_key=vhdl%3AVHDL309)
* [VHDL310 - "case" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL310&rule_key=vhdl%3AVHDL310)

Browse [all new rules](https://demo.linty-services.com/coding_rules?available_since=2023-10-01&languages=vhdl).

### Upgrade Notes

* VHDL168 rule has been removed. Activate its replacement that is able to deal with
  ranges: [VHDL1065 - Choices should not overlap](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1065&rule_key=vhdl%3AVHDL1065)

## 2.0.0

Released on September 19th, 2023.

### Release Notes

Linty now fully supports multi-language (VHDL and Verilog/SystemVerilog) projects.

Built on the latest [SonarQube 10.2.0](https://www.sonarsource.com/products/sonarqube/whats-new/sonarqube-10-2/)
version with support of [Clean Code attributes](https://docs.sonarsource.com/sonarqube/latest/user-guide/clean-code/).

#### VHDL

10 new rules have been added, most of them around clock and reset domains:

* [VHDL1054 - The number of clock domains per design should be as low as possible](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1054&rule_key=vhdl%3AVHDL1054)
* [VHDL1055 - All clocks should be generated within a unique clock management module](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1055&rule_key=vhdl%3AVHDL1055)
* [VHDL1061 - Clock names should be preserved across the design](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1061&rule_key=vhdl%3AVHDL1061)

Browse [all new rules](https://demo.linty-services.com/coding_rules?available_since=2023-09-19&languages=vhdl&selected=vhdl%3AVHDL1055).

### Upgrade Notes

* Request a new [licence key](configure.md#set-linty-license-keys) before upgrading
* Update the following property keys if you set them for some of your projects:
    * `sonar.vhdl.topLevelEntity` => `sonar.hdl.topModule`
    * `sonar.vhdl.file.simulationPaths` => `sonar.hdl.file.simulationPaths`
    * `sonar.vhdl.yosys.hierarchyScriptPath` => `sonar.bugfinder.hierarchyScriptPath`
    * `sonar.vhdl.yosys.readScriptPath` => `sonar.bugfinder.readScriptPath`
    * `sonar.vhdl.yosys.workdir` => `sonar.bugfinder.workdir`

## 1.2.0

Released on July 4th, 2023.

### Release Notes

Built on the latest [SonarQube 10.1.0](https://www.sonarsource.com/products/sonarqube/whats-new/sonarqube-10-1/)
version.

It is now possible to [add custom plugins to the Linty platform](install.md#add-additional-plugins).

#### VHDL

Linty VHDL now highlights, in gray, pieces of code that are not synthesized, adds four new rules:

* [VHDL1050 - Unused entities should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1050&rule_key=vhdl%3AVHDL1050)
* [VHDL1051 - Unused architectures should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1051&rule_key=vhdl%3AVHDL1051)
* [VHDL1052 - Unused generate blocks should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1052&rule_key=vhdl%3AVHDL1052)
* [VHDL1053 - A signal should not be used as both a reset and an enable](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1053&rule_key=vhdl%3AVHDL1053)

and improves existing rules with knowledge of unused code.

#### Verilog

This version integrates BugFinder for Verilog with its first
rule: [VERILOG1000 - Unused modules should be removed](https://demo.linty-services.com/coding_rules?open=verilog%3AVERILOG1000&rule_key=vhdl%3AVERILOG1000)
and adds design graph of each module.

### Upgrade Notes

Split your `build.ys` file into `read.ys` and `hierarchy.ys`. Replace `read -vhdl <my_file>`
with `verific -vhdl <my_file>`. See [Scan Your Code](scan.md#with-bugfinder-and-linter) for further details.

Two distributions of the linty-server Docker image are now available:

* Based
  on [SonarQube Community Edition without branch and pull request support](https://hub.docker.com/r/lintyservices/linty-server)
* Based
  on [SonarQube Developer Edition with branch and pull request support](https://hub.docker.com/r/lintyservices/linty-server-branch-support)

## 1.1.0

Released on April 26th, 2023.

### Release Notes

Built on the latest [SonarQube 10.0.0](https://www.sonarsource.com/products/sonarqube/whats-new/sonarqube-10-0/)
version.

#### VHDL

This version adds two new rules:

* [VHDL1048 - Combinatorial loops should be removed](https://demo.linty-services.com/coding_rules?tags=bug-finder&open=vhdl%3AVHDL1048)
* [VHDL1049 - An entity should not use multiple clocks](https://demo.linty-services.com/coding_rules?tags=bug-finder&open=vhdl%3AVHDL1049)

And generates graphical representations of the design. It is nice, for instance, to easily spot combinatorial loops.

### Upgrade Notes

Follow [uprade guide](install.md#upgrade-linty).

## 1.0.0

Released on March 9th, 2023.

### Release Notes

First official release of the Linty Server as Docker image.

#### VHDL

This version includes [BugFinder](scan_bugfinder.md), a new powerful engine to detect bugs based on synthesized code
analysis. BugFinder rules are tagged as [`bug-finder`](https://demo.linty-services.com/coding_rules?tags=bug-finder)).
There are 47 of them in this first version. Here are some of them:

* [VHDL1001 - All output port of an entity should be connected](https://demo.linty-services.com/coding_rules?tags=bug-finder&open=vhdl%3AVHDL1001)
* [VHDL1004 - All output signals of top-level entity should be registered](https://demo.linty-services.com/coding_rules?tags=bug-finder&open=vhdl%3AVHDL1004)
* [VHDL1017 - Output signals should not be constant](https://demo.linty-services.com/coding_rules?tags=bug-finder&open=vhdl%3AVHDL1017)

Browse all of them on our [demo instance](https://demo.linty-services.com/coding_rules?tags=bug-finder).

Lots of rules have been added or improved. Some rules also changed ID because they were re-implemented with BugFinder.
Thus, we highly recommend you to review your quality profile(s) to (re)activate and configure new rules.