# DO-254 Coverage by Linty Rules

|ID|Title|Automatable|Coverage (full / high / low / none)|Comments|Linty Rules|
|:---:|:---|:---:|:---:|:---|:---|
|**CP1**|Avoid Incorrect VHDL Type Usage|no|none|Synthesis during Linty analysis would fail |
|**CP2**|Avoid Duplicate Signal Assignments|yes|none| |
|**CP3**|Avoid Hard-Coded Numeric Values|yes|full| |[VHDL023: Hardcoded numeric values should be used only in "constant" or "generic"](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL023&#38;rule_key=vhdl%3AVHDL023)<br><br>|
|**CP4**|Avoid Hard-Coded Vector Assignment|yes|full| |[VHDL236: Vector assignments should not be hardcoded](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL236&#38;rule_key=vhdl%3AVHDL236)<br><br>|
|**CP5**|Ensure Consistent FSM State Encoding Style|yes|full| |[VHDL1005: FSM states should be encoded using enumerated type](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1005&#38;rule_key=vhdl%3AVHDL1005)<br><br>|
|**CP6**|Ensure Safe FSM Transitions|yes|low| |[VHDL1040: FSM number of states should equal its type number of states](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1040&#38;rule_key=vhdl%3AVHDL1040)<br><br>|
|**CP7**|Avoid Mismatching Ranges|yes|full| |[VHDL1066: Objects of different lengths should not be compared](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1066&#38;rule_key=vhdl%3AVHDL1066)<br><br>|
|**CP8**|Ensure Complete Sensitivity List|yes|full| |[VHDL1037: The sensitivity list of a process should be minimal](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1037&#38;rule_key=vhdl%3AVHDL1037)<br><br>[VHDL1072: The sensitivity list of a process should be complete](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1072&#38;rule_key=vhdl%3AVHDL1072)<br><br>|
|**CP9**|Ensure Proper Sub-Program Body|yes|full| |[VHDL166: Recursive functions should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL166&#38;rule_key=vhdl%3AVHDL166)<br><br>[VHDL1068: Functions should always return a value](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1068&#38;rule_key=vhdl%3AVHDL1068)<br><br>[VHDL233: Synthesizable functions and procedures should not use external signals and variables](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL233&#38;rule_key=vhdl%3AVHDL233)<br><br>|
|**CP10**|Assign Value Before Using|yes|full| |[VHDL1069: Signals and variables should be assigned a value before being used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1069&#38;rule_key=vhdl%3AVHDL1069)<br><br>|
|**CP11**|Avoid Unconnected Input Ports|yes|full| |[VHDL138: All output ports (and optionally all input ports) of a component should be mapped](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL138&#38;rule_key=vhdl%3AVHDL138)<br><br>|
|**CP12**|Avoid Unconnected Output Ports|yes|full| |[VHDL138: All output ports (and optionally all input ports) of a component should be mapped](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL138&#38;rule_key=vhdl%3AVHDL138)<br><br>|
|**CP13**|Declare Objects Before Use|no|none|Synthesis during Linty analysis would fail |
|**CP14**|Avoid Unused Declarations|yes|full| |[VHDL135: All declared parameters should be used in the corresponding function/procedure](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL135&#38;rule_key=vhdl%3AVHDL135)<br><br>[VHDL134: All declared elements should be used in their corresponding scope](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL134&#38;rule_key=vhdl%3AVHDL134)<br><br>[VHDL1052: Unused generate blocks should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1052&#38;rule_key=vhdl%3AVHDL1052)<br><br>[VHDL1050: Unused entities should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1050&#38;rule_key=vhdl%3AVHDL1050)<br><br>[VHDL1051: Unused architectures should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1051&#38;rule_key=vhdl%3AVHDL1051)<br><br>|
|**CDC1**|Analyze Multiple Asynchronous Clocks|yes|full| |[HDL1000: Track all clock domains](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1000&#38;rule_key=hdl%3AHDL1000)<br><br>[HDL1001: All clock domain crossings (CDC) should be reviewed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1001&#38;rule_key=hdl%3AHDL1001)<br><br>|
|**SS1**|Avoid Implied Logic|yes|low| |[VHDL224: Internal tristates should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL224&#38;rule_key=vhdl%3AVHDL224)<br><br>|
|**SS2**|Ensure Proper Case Statement Specification|yes|full|'Be complete' would be caught at synthesis step of Linty analysis |[VHDL1065: Choices should not overlap](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1065&#38;rule_key=vhdl%3AVHDL1065)<br><br>[VHDL1064: Choices outside of range should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1064&#38;rule_key=vhdl%3AVHDL1064)<br><br>[VHDL003: Each case statement should define an "others" clause](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL003&#38;rule_key=vhdl%3AVHDL003)<br><br>|
|**SS3**|Avoid Combinational Feedback|yes|full| |[HDL1003: Combinatinoal loops should be removed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1003&#38;rule_key=hdl%3AHDL1003)<br><br>|
|**SS4**|Avoid Latch Inference|yes|full| |[HDL1043: Latches should be removed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1043&#38;rule_key=hdl%3AHDL1043)<br><br>[VHDL1036: "if" statements should always contain an "else" statement in combinational processes to avoid undesired latch inference](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1036&#38;rule_key=vhdl%3AVHDL1036)<br><br>|
|**SS5**|Avoid Multiple Waveforms|yes|full| |[VHDL235: Signal assignments should not contain multiple waveforms](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL235&#38;rule_key=vhdl%3AVHDL235)<br><br>|
|**SS6**|Avoid Multiple Drivers|yes|full| |[VHDL140: Concurrent assignments should be complete to avoid undesired latch inference](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL140&#38;rule_key=vhdl%3AVHDL140)<br><br>[VHDL139: Signals and variables should not be assigned in multiple processes or equivalent concurrent assignments](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL139&#38;rule_key=vhdl%3AVHDL139)<br><br>|
|**SS7**|Avoid Uninitialized VHDL Deferred Constants|yes|full| |[VHDL155: All deferred constants should be initialized](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL155&#38;rule_key=vhdl%3AVHDL155)<br><br>|
|**SS8**|Avoid Clock Used as Data|yes|high| |[VHDL1012: Clock signals not used as clock of a flip-flop should be reviewed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1012&#38;rule_key=vhdl%3AVHDL1012)<br><br>|
|**SS9**|Avoid Shared Clock and Reset Signal|yes|high| |[VHDL1033: Reset signals not used as reset of a flip-flop should be reviewed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1033&#38;rule_key=vhdl%3AVHDL1033)<br><br>[VHDL1012: Clock signals not used as clock of a flip-flop should be reviewed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1012&#38;rule_key=vhdl%3AVHDL1012)<br><br>|
|**SS10**|Avoid Gated Clocks|yes|none| |
|**SS11**|Avoid Internally Generated Clocks|yes|none| |
|**SS12**|Avoid Internally Generated Resets|yes|none| |
|**SS13**|Avoid Mixed Polarity Reset|yes|full| |[HDL1035: Active-high resets should be preferred over active-low resets](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1035&#38;rule_key=hdl%3AHDL1035)<br><br>[HDL1036: Active-low resets should be preferred over active-high resets](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1036&#38;rule_key=hdl%3AHDL1036)<br><br>|
|**SS14**|Avoid Unresettable Registers|yes|none| |
|**SS15**|Avoid Asynchronous Reset Release|yes|none| |
|**SS16**|Avoid Initialization Assignments|yes|none| |
|**SS17**|Avoid Undriven and Unused Logic|no|none| |
|**SS18**|Ensure Register Controllability|yes|none| |
|**SS19**|Avoid Snake Paths|yes|low| |[VHDL172: Conditional branching statements ("if", "case", "while" and "for" loops) should not be too deeply nested](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL172&#38;rule_key=vhdl%3AVHDL172)<br><br>|
|**SS20**|Ensure Nesting Limits|yes|full| |[VHDL172: Conditional branching statements ("if", "case", "while" and "for" loops) should not be too deeply nested](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL172&#38;rule_key=vhdl%3AVHDL172)<br><br>|
|**SS21**|Ensure Consistent Vector Order|yes|full| |[VHDL036: Vector direction in ranges should always be the same](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL036&#38;rule_key=vhdl%3AVHDL036)<br><br>|
|**DR1**|Use Statement Labels|yes|low| |[VHDL213: Processes should be identified by labels](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL213&#38;rule_key=vhdl%3AVHDL213)<br><br>|
|**DR2**|Avoid Mixed Case Naming for Differentiation|yes|full| |[VHDL136: All references should have the same case as the corresponding declarations](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL136&#38;rule_key=vhdl%3AVHDL136)<br><br>|
|**DR3**|Ensure Unique Name Spaces|yes|full| |[VHDL209: Type/Subtype names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL209&#38;rule_key=vhdl%3AVHDL209)<br><br>[VHDL016: Signal names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL016&#38;rule_key=vhdl%3AVHDL016)<br><br>[VHDL015: Constant names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL015&#38;rule_key=vhdl%3AVHDL015)<br><br>[VHDL012: Function names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL012&#38;rule_key=vhdl%3AVHDL012)<br><br>[VHDL007: Architecture names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL007&#38;rule_key=vhdl%3AVHDL007)<br><br>[VHDL009: Entity names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL009&#38;rule_key=vhdl%3AVHDL009)<br><br>[VHDL008: Configuration names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL008&#38;rule_key=vhdl%3AVHDL008)<br><br>[VHDL234: Variable names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL234&#38;rule_key=vhdl%3AVHDL234)<br><br>[VHDL199: Procedure names should be unique in a project](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL199&#38;rule_key=vhdl%3AVHDL199)<br><br>|
|**DR4**|Use Separate Declaration Style|yes|full| |[VHDL126: Multiple declarations should not be written on the same line](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL126&#38;rule_key=vhdl%3AVHDL126)<br><br>|
|**DR5**|Use Separate Statement Style|yes|full| |[VHDL161: Statements should be on separate lines](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL161&#38;rule_key=vhdl%3AVHDL161)<br><br>|
|**DR6**|Ensure Consistent Indentation|yes|low| |[VHDL210: Port clauses should be properly formatted](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL210&#38;rule_key=vhdl%3AVHDL210)<br><br>|
|**DR7**|Avoid Using Tabs|yes|full| |[HDL004: Tabulation characters should not be used](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL004&#38;rule_key=hdl%3AHDL004)<br><br>|
|**DR8**|Avoid Large Design Files|yes|full| |[VHDL033: Files should not have too many lines of code](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL033&#38;rule_key=vhdl%3AVHDL033)<br><br>|
|**DR9**|Ensure Consistent Signal Names Across Hierarchy|yes|none| |
|**DR10**|Ensure Consistent File Header|yes|full| |[VHDL239: File header should match a template](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL239&#38;rule_key=vhdl%3AVHDL239)<br><br>|
|**DR11**|Ensure Sufficient Comment Density|yes|full| |[VHDL160: Declarations should be commented](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL160&#38;rule_key=vhdl%3AVHDL160)<br><br>[VHDL207: Processes should be commented](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL207&#38;rule_key=vhdl%3AVHDL207)<br><br>[VHDL307: Code should be properly commented](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL307&#38;rule_key=vhdl%3AVHDL307)<br><br>|
|**DR12**|Ensure Proper Placement of Comments|yes|full| |[VHDL194: Trailing comments should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL194&#38;rule_key=vhdl%3AVHDL194)<br><br>|
|**DR13**|Ensure Company Specific Naming Standards|yes|full| |[HDL1028: FSM state signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1028&#38;rule_key=hdl%3AHDL1028)<br><br>[VHDL1026: Reset signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1026&#38;rule_key=vhdl%3AVHDL1026)<br><br>[VHDL181: Alias names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL181&#38;rule_key=vhdl%3AVHDL181)<br><br>[VHDL187: "for" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL187&#38;rule_key=vhdl%3AVHDL187)<br><br>[VHDL1035: Process labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1035&#38;rule_key=vhdl%3AVHDL1035)<br><br>[VHDL171: Package names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL171&#38;rule_key=vhdl%3AVHDL171)<br><br>[VHDL1009: Clock signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1009&#38;rule_key=vhdl%3AVHDL1009)<br><br>[VHDL309: "if" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL309&#38;rule_key=vhdl%3AVHDL309)<br><br>[VHDL310: "case" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL310&#38;rule_key=vhdl%3AVHDL310)<br><br>[VHDL010: Entity names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL010&#38;rule_key=vhdl%3AVHDL010)<br><br>[VHDL131: Procedure names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL131&#38;rule_key=vhdl%3AVHDL131)<br><br>[VHDL130: Function names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL130&#38;rule_key=vhdl%3AVHDL130)<br><br>[VHDL005: Architecture names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL005&#38;rule_key=vhdl%3AVHDL005)<br><br>[VHDL006: Configuration names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL006&#38;rule_key=vhdl%3AVHDL006)<br><br>[VHDL120: Generic parameter names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL120&#38;rule_key=vhdl%3AVHDL120)<br><br>[VHDL122: Type names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL122&#38;rule_key=vhdl%3AVHDL122)<br><br>[VHDL121: Subtype names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL121&#38;rule_key=vhdl%3AVHDL121)<br><br>[VHDL117: Constant names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL117&#38;rule_key=vhdl%3AVHDL117)<br><br>[VHDL116: Variable names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL116&#38;rule_key=vhdl%3AVHDL116)<br><br>[VHDL119: Signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL119&#38;rule_key=vhdl%3AVHDL119)<br><br>[VHDL118: Port names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL118&#38;rule_key=vhdl%3AVHDL118)<br><br>|