# CNES Coverage by Linty Rules
|ID|Title|Automatable|Coverage (full / high / low / none)|Comments|Linty Rules|
|:---:|:---|:---:|:---:|:---|:---|
|**[STD‑00100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|VHDL object naming convention|yes|full| |[VHDL1026: Reset signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1026&rule_key=vhdl%3AVHDL1026)
[VHDL181: Alias names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL181&rule_key=vhdl%3AVHDL181)
[VHDL187: "for" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL187&rule_key=vhdl%3AVHDL187)
[VHDL1035: Process labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1035&rule_key=vhdl%3AVHDL1035)
[VHDL171: Package names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL171&rule_key=vhdl%3AVHDL171)
[VHDL173: Instance names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL173&rule_key=vhdl%3AVHDL173)
[VHDL1009: Clock signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1009&rule_key=vhdl%3AVHDL1009)
[VHDL309: "if" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL309&rule_key=vhdl%3AVHDL309)
[VHDL310: "case" generate statement labels should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL310&rule_key=vhdl%3AVHDL310)
[VHDL010: Entity names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL010&rule_key=vhdl%3AVHDL010)
[VHDL131: Procedure names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL131&rule_key=vhdl%3AVHDL131)
[VHDL130: Function names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL130&rule_key=vhdl%3AVHDL130)
[VHDL005: Architecture names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL005&rule_key=vhdl%3AVHDL005)
[VHDL006: Configuration names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL006&rule_key=vhdl%3AVHDL006)
[VHDL120: Generic parameter names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL120&rule_key=vhdl%3AVHDL120)
[VHDL122: Type names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL122&rule_key=vhdl%3AVHDL122)
[VHDL121: Subtype names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL121&rule_key=vhdl%3AVHDL121)
[VHDL117: Constant names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL117&rule_key=vhdl%3AVHDL117)
[VHDL116: Variable names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL116&rule_key=vhdl%3AVHDL116)
[VHDL119: Signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL119&rule_key=vhdl%3AVHDL119)
[VHDL118: Port names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL118&rule_key=vhdl%3AVHDL118)
|
|**[STD‑00200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Name of clock signal|yes|full| |[VHDL1009: Clock signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1009&rule_key=vhdl%3AVHDL1009)
|
|**[STD‑00300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Name of reset signal|yes|full| |[VHDL1026: Reset signal names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1026&rule_key=vhdl%3AVHDL1026)
|
|**[STD‑00400](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Label for process|yes|full| |[VHDL213: Processes should be identified by labels](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL213&rule_key=vhdl%3AVHDL213)
|
|**[STD‑00500](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Name of signal relation with behaviour|no|none| |
|**[STD‑00600](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|VHDL file extension|yes|full| |[VHDL180: File name should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL180&rule_key=vhdl%3AVHDL180)
|
|**[STD‑00701](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Preservation of signal name inside an entity|yes|none| |
|**[STD‑00800](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|File name convention|yes|full| |[VHDL180: File name should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL180&rule_key=vhdl%3AVHDL180)
[VHDL010: Entity names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL010&rule_key=vhdl%3AVHDL010)
|
|**[STD‑00900](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|File name of an entity|yes|full| |[VHDL180: File name should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL180&rule_key=vhdl%3AVHDL180)
[VHDL010: Entity names should comply with a naming convention](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL010&rule_key=vhdl%3AVHDL010)
|
|**[STD‑01000](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Number of entities per file|yes|full| |[VHDL218: A file should not define more than one entity](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL218&rule_key=vhdl%3AVHDL218)
|
|**[STD‑01100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Number of architectures in files|yes|full| |[VHDL019: Each file should define only one single architecture](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL019&rule_key=vhdl%3AVHDL019)
|
|**[STD‑01200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Number of statements per line|yes|full| |[VHDL161: Statements should be on separate lines](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL161&rule_key=vhdl%3AVHDL161)
[VHDL126: Multiple declarations should not be written on the same line](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL126&rule_key=vhdl%3AVHDL126)
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|**[STD‑01300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Number of ports declaration per line|yes|full| |[VHDL137: Only one port should be declared or mapped on each line](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL137&rule_key=vhdl%3AVHDL137)
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|**[STD‑01400](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Instantiation of components|yes|full| |[VHDL189: End block identifier should be repeated at the end](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL189&rule_key=vhdl%3AVHDL189)
[VHDL188: Instantiations should be done by name, not by position](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL188&rule_key=vhdl%3AVHDL188)
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|**[STD‑01500](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Entity ports convention|no|none|Generic rule of STD-01600 and STD-01700 |
|**[STD‑01600](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Entity port sort|no|none| |
|**[STD‑01700](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Entity special ports|yes|none| |
|**[STD‑01800](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Primitive isolation|no|none| |
|**[STD‑01900](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Indentation of source code|yes|low| |[VHDL210: Port clauses should be properly formatted](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL210&rule_key=vhdl%3AVHDL210)
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|**[STD‑02000](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Indentation style|yes|full| |[HDL004: Tabulation characters should not be used](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL004&rule_key=hdl%3AHDL004)
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|**[STD‑02100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Compactness of VHDL source code|yes|full| |[VHDL033: Files should not have too many lines of code](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL033&rule_key=vhdl%3AVHDL033)
[VHDL149: Extended identifiers should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL149&rule_key=vhdl%3AVHDL149)
|
|**[STD‑02200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Version control in header of file|yes|full| |[VHDL239: File header should match a template](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL239&rule_key=vhdl%3AVHDL239)
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|**[STD‑02300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Copyright information in the header of file|yes|full| |[VHDL239: File header should match a template](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL239&rule_key=vhdl%3AVHDL239)
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|**[STD‑02400](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Creation information in the header of the file|yes|full| |[VHDL239: File header should match a template](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL239&rule_key=vhdl%3AVHDL239)
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|**[STD‑02500](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Functional information in the header of file|yes|full| |[VHDL239: File header should match a template](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL239&rule_key=vhdl%3AVHDL239)
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|**[STD‑02600](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|IEEE libraries preference|yes|full| |[VHDL211: Synopsys "std_logic_arith", "std_logic_signed" and "std_logic_unsigned" libraries should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL211&rule_key=vhdl%3AVHDL211)
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|**[STD‑02700](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Default language|yes|full|Headers and comments checked. Not possible to check code (such as entity names, signal names, etc.). It would lead to too many false positives. |[VHDL225: Comments should be written in a specified language / Commented-out code should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL225&rule_key=vhdl%3AVHDL225)
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|**[STD‑02800](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Comment strategy|yes|full|Comment density only as the relevance of comments cannot be automated |
|**[STD‑02900](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Comments for entity ports|yes|full| |[VHDL163: Entity ports should be commented](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL163&rule_key=vhdl%3AVHDL163)
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|**[STD‑03000](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Comments for objects declaration and statements|yes|high| |[VHDL160: Declarations should be commented](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL160&rule_key=vhdl%3AVHDL160)
[VHDL207: Processes should be commented](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL207&rule_key=vhdl%3AVHDL207)
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|**[STD‑03100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Dead VHDL code|yes|high| |[VHDL135: All declared parameters should be used in the corresponding function/procedure](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL135&rule_key=vhdl%3AVHDL135)
[VHDL134: All declared elements should be used in their corresponding scope](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL134&rule_key=vhdl%3AVHDL134)
[VHDL1052: Unused generate blocks should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1052&rule_key=vhdl%3AVHDL1052)
[VHDL1050: Unused entities should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1050&rule_key=vhdl%3AVHDL1050)
[VHDL1051: Unused architectures should be removed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1051&rule_key=vhdl%3AVHDL1051)
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|**[STD‑03200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unused output ports components management|yes|low|Does not check unused ports |[VHDL138: All output ports (and optionally all input ports) of a component should be mapped](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL138&rule_key=vhdl%3AVHDL138)
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|**[STD‑03300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Buffer port type|yes|full| |[VHDL025: Only allowed port modes should be used: 'in', 'out' and, for top-level entities only, 'inout'](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL025&rule_key=vhdl%3AVHDL025)
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|**[STD‑03400](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Top level ports|yes|full| |[VHDL026: Only allowed port types should be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL026&rule_key=vhdl%3AVHDL026)
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|**[STD‑03500](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Record type for top level entity ports|yes|full| |[VHDL026: Only allowed port types should be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL026&rule_key=vhdl%3AVHDL026)
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|**[STD‑03600](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Reset sensitive level|yes|full| |[HDL1035: Active-high resets should be preferred over active-low resets](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1035&rule_key=hdl%3AHDL1035)
[HDL1036: Active-low resets should be preferred over active-high resets](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1036&rule_key=hdl%3AHDL1036)
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|**[STD‑03700](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Reset assertion and deassertion|yes|none| |
|**[STD‑03800](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Synchronous elements initialization|yes|none| |
|**[STD‑03900](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|State machine type definition|yes|full| |[VHDL1005: FSM states should be encoded using enumerated type](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1005&rule_key=vhdl%3AVHDL1005)
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|**[STD‑04000](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|State machine case enumeration completion|yes|full| |[VHDL003: Each case statement should define an "others" clause](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL003&rule_key=vhdl%3AVHDL003)
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|**[STD‑04100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Clock domain crossing|yes|full| |[HDL1000: Track all clock domains](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1000&rule_key=hdl%3AHDL1000)
[HDL1001: All clock domain crossings (CDC) should be reviewed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1001&rule_key=hdl%3AHDL1001)
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|**[STD‑04200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Clock domain crossing handshake based|yes|none| |
|**[STD‑04300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Clock domain crossing FIFOs based|yes|none| |
|**[STD‑04400](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Clock management module|yes|full| |[HDL1013: All clocks should be generated within a unique clock management module](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1013&rule_key=hdl%3AHDL1013)
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|**[STD‑04500](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of Clock Reassignment|yes|full| |[VHDL1012: Clock signals not used as clock of a flip-flop should be reviewed](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1012&rule_key=vhdl%3AVHDL1012)
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|**[STD‑04600](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Clock domain number in the design|yes|full| |[HDL1002: The number of clock domains per design should be as low as possible](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1002&rule_key=hdl%3AHDL1002)
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|**[STD‑04700](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Number of clock domains per modules|yes|high| |[VHDL1049: An entity should not use multiple clocks](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1049&rule_key=vhdl%3AVHDL1049)
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|**[STD‑04800](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Clock edge sensitivity|yes|full| |[HDL1041: Falling should be preferred over rising to detect clock transitions](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1041&rule_key=hdl%3AHDL1041)
[HDL1042: Rising should be preferred over falling to detect clock transitions](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1042&rule_key=hdl%3AHDL1042)
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|**[STD‑04900](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Edge detection best practice|yes|none| |
|**[STD‑05000](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Sensitivity list for synchronous processes|yes|full| |[VHDL1037: The sensitivity list of a process should be minimal](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1037&rule_key=vhdl%3AVHDL1037)
[VHDL1072: The sensitivity list of a process should be complete](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1072&rule_key=vhdl%3AVHDL1072)
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|**[STD‑05100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Metastability management|yes|none| |
|**[STD‑05200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Output signal registration|yes|full| |[HDL1008: All output signals of top-level module should be registered](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1008&rule_key=hdl%3AHDL1008)
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|**[STD‑05300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Sensitivity list for combinational processes|yes|full| |[VHDL1037: The sensitivity list of a process should be minimal](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1037&rule_key=vhdl%3AVHDL1037)
[VHDL1072: The sensitivity list of a process should be complete](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1072&rule_key=vhdl%3AVHDL1072)
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|**[STD‑05400](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of internal tristate|yes|full| |[VHDL224: Internal tristates should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL224&rule_key=vhdl%3AVHDL224)
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|**[STD‑05500](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of latches|yes|full| |[HDL1043: Latches should be removed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1043&rule_key=hdl%3AHDL1043)
[VHDL1036: "if" statements should always contain an "else" statement in combinational processes to avoid undesired latch inference](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1036&rule_key=vhdl%3AVHDL1036)
[VHDL1037: The sensitivity list of a process should be minimal](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1037&rule_key=vhdl%3AVHDL1037)
[VHDL140: Concurrent assignments should be complete to avoid undesired latch inference](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL140&rule_key=vhdl%3AVHDL140)
[VHDL1072: The sensitivity list of a process should be complete](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1072&rule_key=vhdl%3AVHDL1072)
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|**[STD‑05600](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of combinational feedbacks|yes|full| |[HDL1003: Combinatinoal loops should be removed](https://demo.linty-services.com/coding_rules?open=hdl%3AHDL1003&rule_key=hdl%3AHDL1003)
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|**[STD‑05700](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of gated clocks|yes|none| |
|**[STD‑05800](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Use of VHDL types in RTL design|yes|full| |[VHDL1005: FSM states should be encoded using enumerated type](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1005&rule_key=vhdl%3AVHDL1005)
[VHDL303: Only synthesizable types should be used in design](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL303&rule_key=vhdl%3AVHDL303)
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|**[STD‑05900](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Range for integers|yes|full| |[VHDL029: 'integer', 'natural' and 'positive' declarations should have range constraint](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL029&rule_key=vhdl%3AVHDL029)
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|**[STD‑06000](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Range direction for arrays|yes|full| |[VHDL164: Range direction in array definitions should always be the same](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL164&rule_key=vhdl%3AVHDL164)
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|**[STD‑06100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Range direction for std_logic_vector|yes|full| |[VHDL036: Vector direction in ranges should always be the same](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL036&rule_key=vhdl%3AVHDL036)
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|**[STD‑06200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Management of numeric values|yes|high| |[VHDL023: Hardcoded numeric values should be used only in "constant" or "generic"](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL023&rule_key=vhdl%3AVHDL023)
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|**[STD‑06300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of variables in RTL design|yes|low| |[VHDL308: Variables should not be used](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL308&rule_key=vhdl%3AVHDL308)
[VHDL190: Variables should only be used in processes, functions and procedures](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL190&rule_key=vhdl%3AVHDL190)
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|**[STD‑06400](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Error mitigation strategy|no|none|Generic rule |
|**[STD‑06500](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Counters end of counting|yes|none| |
|**[STD‑06600](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Dimension of comparison elements|yes|full| |[VHDL1066: Objects of different lengths should not be compared](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL1066&rule_key=vhdl%3AVHDL1066)
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|**[STD‑06700](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of wait statement in RTL design|yes|full| |[VHDL183: Non-synthesizable statements should not be used in design](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL183&rule_key=vhdl%3AVHDL183)
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|**[STD‑06800](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of signal initialization in declaration section|yes|full| |[VHDL032: Signals should not be initialized in their declaration](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL032&rule_key=vhdl%3AVHDL032)
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|**[STD‑06900](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Unsuitability of procedures and functions in RTL design|yes|full| |[VHDL206: Functions and procedures should not be used in design](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL206&rule_key=vhdl%3AVHDL206)
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|**[STD‑07000](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Maximum depths of nested objects|yes|high| |[VHDL172: Conditional branching statements ("if", "case", "while" and "for" loops) should not be too deeply nested](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL172&rule_key=vhdl%3AVHDL172)
[VHDL152: Packages should not be too deeply nested](https://demo.linty-services.com/coding_rules?open=vhdl%3AVHDL152&rule_key=vhdl%3AVHDL152)
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|**[STD‑07100](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Simulation ending|yes|none| |
|**[STD‑07200](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Use of procedures and functions in testbenches|no|none|Generic rule |
|**[STD‑07300](https://github.com/VHDLTool/VHDL_Handbook_STD/releases/download/STD_V2.1/handbook_STD_Edition_V2.1.pdf)**|Use of wait statement in testbenches|yes|none| |